some modelsmain

19 files changed, 234 insertions, 0 deletions

diff --git a/.gitignore b/.gitignore
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--- /dev/null
+++ b/.gitignore
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+# -*- mode: gitignore; -*-
+*~
+\#*\#
+/.emacs.desktop
+/.emacs.desktop.lock
+*.elc
+auto-save-list
+tramp
+.\#*
+
+# Org-mode
+.org-id-locations
+*_archive
+
+# flymake-mode
+*_flymake.*
+
+# eshell files
+/eshell/history
+/eshell/lastdir
+
+# elpa packages
+/elpa/
+
+# reftex files
+*.rel
+
+# AUCTeX auto folder
+/auto/
+
+# cask packages
+.cask/
+dist/
+
+# Flycheck
+flycheck_*.el
+
+# server auth directory
+/server/
+
+# projectiles files
+.projectile
+
+# directory configuration
+.dir-locals.el
+
+# network security
+/network-security.data
+
+# undo-tree
+*.~undo-tree~
diff --git a/i8288.v b/i8288.v
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index 0000000..83a5247
--- /dev/null
+++ b/i8288.v
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+module i8288
+  (input IOB,
+   input CLK,
+   input nS1);
+
+
+endmodule; // i8288
diff --git a/sn7400.v b/sn7400.v
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index 0000000..a08ab06
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+++ b/sn7400.v
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+`timescale 1ns/1ps
+module sn7400
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [3:0]	A,
+   input [3:0]	B,
+   output [3:0]	Y);
+
+   assign #(tPLH, tPHL) Y = ~(A & B);
+endmodule
diff --git a/sn7401.v b/sn7401.v
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+++ b/sn7401.v
@@ -0,0 +1,9 @@
+`timescale 1ps/1ns
+module sn7401
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [3:0]	A,
+   input [3:0]	B,
+   output [3:0]	Y);
+
+   assign #(tPLH, tPHL) (strong0, highz1) Y[i] = ~(A[i] & B[i]);
+endmodule
diff --git a/sn7402.v b/sn7402.v
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index 0000000..bddc3b9
--- /dev/null
+++ b/sn7402.v
@@ -0,0 +1,9 @@
+`timescale 1ns/1ps
+module sn7402
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [3:0]	A,
+   input [3:0]	B,
+   output [3:0]	Y);
+
+   assign #(tPLH, tPHL) Y = ~(A | B);
+endmodule
diff --git a/sn7404.v b/sn7404.v
new file mode 100644
index 0000000..58bd2a7
--- /dev/null
+++ b/sn7404.v
@@ -0,0 +1,8 @@
+`timescale 1ns/1ps
+module sn7404
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [5:0]	A,
+   output [5:0]	Y);
+
+   assign #(tPLH, tPHL) Y = ~A;
+endmodule
diff --git a/sn7405.v b/sn7405.v
new file mode 100644
index 0000000..8a6f22c
--- /dev/null
+++ b/sn7405.v
@@ -0,0 +1,8 @@
+`timescale 1ns/1ps
+module sn7405
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [5:0]	A,
+   output [5:0]	Y);
+
+   assign #(tPLH, tPHL) (strong0, highz1) Y[i] = ~A[i];
+endmodule
diff --git a/sn7408.v b/sn7408.v
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index 0000000..63b0a87
--- /dev/null
+++ b/sn7408.v
@@ -0,0 +1,9 @@
+`timescale 1ns/1ps
+module sn7408
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [3:0]	A,
+   input [3:0]	B,
+   output [3:0]	Y);
+
+   assign #(tPLH, tPHL) Y = A & B;
+endmodule
diff --git a/sn7409.v b/sn7409.v
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index 0000000..e577393
--- /dev/null
+++ b/sn7409.v
@@ -0,0 +1,9 @@
+`timescale 1ps/1ns
+module sn7409
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [3:0]	A,
+   input [3:0]	B,
+   output [3:0]	Y);
+   
+   assign #(tPLH, tPHL) (strong0, highz1) Y = A & B;
+endmodule
diff --git a/sn7410.v b/sn7410.v
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index 0000000..65e690f
--- /dev/null
+++ b/sn7410.v
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+`timescale 1ns/1ps
+module sn7410
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [2:0]	A,
+   input [2:0]	B,
+   input [2:0]  C,
+   output [2:0]	Y);
+
+   assign #(tPLH, tPHL) Y = ~(A & B & C);
+endmodule
diff --git a/sn7411.v b/sn7411.v
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index 0000000..3e65579
--- /dev/null
+++ b/sn7411.v
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+`timescale 1ns/1ps
+module sn7411
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [2:0]	A,
+   input [2:0]	B,
+   input [2:0]  C,
+   output [2:0]	Y);
+
+   assign #(tPLH, tPHL) Y = A & B & C;
+endmodule
diff --git a/sn7415.v b/sn7415.v
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index 0000000..eeee05a
--- /dev/null
+++ b/sn7415.v
@@ -0,0 +1,10 @@
+`timescale 1ns/1ps
+module sn7415
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [2:0]	A,
+   input [2:0]	B,
+   input [2:0]  C,
+   output [2:0]	Y);
+
+   assign #(tPLH, tPHL) (strong0, highz1) Y = A & B & C;
+endmodule
diff --git a/sn7420.v b/sn7420.v
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index 0000000..cca3fcd
--- /dev/null
+++ b/sn7420.v
@@ -0,0 +1,11 @@
+`timescale 1ns/1ps
+module sn7420
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [1:0]	A,
+   input [1:0]	B,
+   input [1:0]	C,
+   input [1:0]	D,
+   output [1:0]	Y);
+
+   assign #(tPLH, tPHL) Y = ~(A & B & C & D);
+endmodule
diff --git a/sn7421.v b/sn7421.v
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index 0000000..08b40b8
--- /dev/null
+++ b/sn7421.v
@@ -0,0 +1,11 @@
+`timescale 1ns/1ps
+module sn7421
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [1:0]	A,
+   input [1:0]	B,
+   input [1:0]	C,
+   input [1:0]	D,
+   output [1:0]	Y);
+
+   assign #(tPLH, tPHL) Y = A & B & C & D;
+endmodule
diff --git a/sn7422.v b/sn7422.v
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index 0000000..7855b70
--- /dev/null
+++ b/sn7422.v
@@ -0,0 +1,11 @@
+`timescale 1ns/1ps
+module sn7422
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [1:0]	A,
+   input [1:0]	B,
+   input [1:0]	C,
+   input [1:0]	D,
+   output [1:0]	Y);
+
+   assign #(tPLH, tPHL) (strong0, highz1) Y = ~(A & B & C & D);
+endmodule
diff --git a/sn7423.v b/sn7423.v
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index 0000000..2f8db87
--- /dev/null
+++ b/sn7423.v
@@ -0,0 +1,15 @@
+`timescale 1ns/1ps
+module sn7423
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [1:0]	A,
+   input [1:0]	B,
+   input [1:0]	C,
+   input [1:0]	D,
+   input [1:0]	G,
+   input	X,
+   output [1:0]	Y);
+
+   wire [1:0] Xt;
+   assign Xt = {0, X};
+   assign #(tPLH, tPHL) Y = ~((G & (A | B | C | D)) | Xt);
+endmodule
diff --git a/sn7425.v b/sn7425.v
new file mode 100644
index 0000000..6ac9bb5
--- /dev/null
+++ b/sn7425.v
@@ -0,0 +1,12 @@
+`timescale 1ns/1ps
+module sn7423
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [1:0]	A,
+   input [1:0]	B,
+   input [1:0]	C,
+   input [1:0]	D,
+   input [1:0]	G,
+   output [1:0]	Y);
+
+   assign #(tPLH, tPHL) Y = ~(G & (A | B | C | D));
+endmodule
diff --git a/sn7427.v b/sn7427.v
new file mode 100644
index 0000000..67f1a41
--- /dev/null
+++ b/sn7427.v
@@ -0,0 +1,10 @@
+`timescale 1ns/1ps
+module sn7427
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [2:0]	A,
+   input [2:0]	B,
+   input [2:0]  C,
+   output [2:0]	Y);
+
+   assign #(tPLH, tPHL) Y = ~(A | B | C);
+endmodule
diff --git a/sn7430.v b/sn7430.v
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index 0000000..425b7ab
--- /dev/null
+++ b/sn7430.v
@@ -0,0 +1,15 @@
+`timescale 1ns/1ps
+module sn7430
+  #(parameter tPLH = 0, tPHL = 0)
+  (input  A,
+   input  B,
+   input  C,
+   input  D,
+   input  E,
+   input  F,
+   input  G,
+   input  H,
+   output Y);
+
+   assign #(tPLH, tPHL) Y = ~(A & B & C & D & E & F & G & H);
+endmodule