some modelsmain

1 files changed, 15 insertions, 0 deletions

diff --git a/sn7423.v b/sn7423.v
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+++ b/sn7423.v
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+`timescale 1ns/1ps
+module sn7423
+  #(parameter tPLH = 0, tPHL = 0)
+  (input [1:0]	A,
+   input [1:0]	B,
+   input [1:0]	C,
+   input [1:0]	D,
+   input [1:0]	G,
+   input	X,
+   output [1:0]	Y);
+
+   wire [1:0] Xt;
+   assign Xt = {0, X};
+   assign #(tPLH, tPHL) Y = ~((G & (A | B | C | D)) | Xt);
+endmodule